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CY62177DV30 MoBL(R)
32-Mbit (2M x 16) Static RAM
Features
* Very high speed: 55 ns and 70 ns * Wide voltage range: 2.20V-3.60V * Ultra-low active power -- Typical active current: 2 mA @ f = 1 MHz -- Typical active current: 15 mA @ f = fmax * Ultra low standby power * Easy memory expansion with CE1, CE2 and OE features * Automatic power-down when deselected * CMOS for optimum speed/power * Packages offered in a 48-ball FBGA reduces power consumption. The device can also be put into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected (CE1HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). Writing to the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A20). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A20). Reading from the device is accomplished by taking Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes.
Functional Description[1]
The CY62177DV30 is a high-performance CMOS static RAM organized as 2M words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications such as cellular telephones.The device also has an automatic power-down feature that significantly
Logic Block Diagram
DATA-IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER
2048K x 16 RAM Array
SENSE AMPS
I/O0-I/O7 I/O8-I/O15
COLUMN DECODER
BHE WE OE BLE
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20
CE2
CE1
Power-down Circuit
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05633 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised June 14, 2006
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CY62177DV30 MoBL(R)
Pin Configuration[2]
FBGA
Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A18 2 OE BHE I/O10 I/O11 3 A0 A3 A5 A17 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE1 I/O1 I/O3 I/O4 I/O5 WE A11 6 CE2 I/O0 I/O2 Vcc Vss I/O6 I/O7 A20 A B C D E F G H
I/O12 DNU I/O13 A19 A8 A14 A12 A9
Product Portfolio
Power Dissipation Operating ICC(mA) VCC Range (V) Product CY62177DV30L CY62177DV30LL Min. 2.20 Typ.[3] 3.0 Max. 3.60 Speed (ns) 55 70 55 70 2 4 f = 1 MHz Typ.[3] 2 Max. 4 15 12 15 12 f = fmax Typ.[3] Max. 30 25 30 25 5 50 Standby ISB2(A) Typ.[3] 5 Max. 60
Notes: 2. DNU pins have to be left floating or tied to Vss to ensure proper application. 3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied............................................ -55C to + 125C Supply Voltage to Ground Potential .......-0.3V to VCC + 0.3V DC Voltage Applied to Outputs in High Z State[4, 5] .................................-0.3V to VCC + 0.3V DC Input Voltage[4, 5] .............................-0.3V to VCC + 0.3V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA
Operating Range
Device CY62177DV30L CY62177DV30LL Range Ambient Temperature VCC[6] 2.20V to 3.60V
Industrial -40C to +85C
Electrical Characteristics Over the Operating Range
CY62177DV30-55 Parameter VOH VOL VIH Description Output HIGH Voltage Output LOW Voltage Test Conditions IOH = -0.1 mA IOH = -1.0 mA IOL = 0.1 mA IOL = 2.1mA VCC = 2.20V VCC = 2.70V VCC = 2.20V VCC = 2.70V 1.8 2.2 -0.3 -0.3 -1 -1 15 2 5 5 Min. 2.0 2.4 0.4 0.4 VCC +0.3V VCC +0.3V 0.6 0.8 +1 +1 30 4 100 100 1.8 2.2 -0.3 -0.3 -1 -1 12 2 5 5 Typ.[3] Max. CY62177DV30-70 Min. 2.0 2.4 0.4 0.4 VCC +0.3V VCC +0.3V 0.6 0.8 +1 +1 25 4 100 100 Typ.[3] Max. Unit V V V V V V V V A A mA mA A
Input HIGH Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V
VIL IIX IOZ ICC
Input LOW Voltage VCC = 2.2V to 2.7V VCC= 2.7V to 3.6V Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current--CMOS Inputs Automatic CE Power-Down Current--CMOS Inputs GND < VI < VCC GND < VO < VCC, Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = VCCmax IOUT = 0 mA CMOS levels
ISB1
CE1 > VCC-0.2V, CE2 < 0.2V, L VIN > VCC-0.2V, VIN < 0.2V) LL f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.60V CE1 > VCC - 0.2V, CE2 < 0.2V, L VIN > VCC - 0.2V or VIN < 0.2V, LL f = 0, VCC = 3.60V
ISB2
5 5
60 50
5 5
60 50
A
Notes: 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. VIH(Max) = VCC + 0.75V for pulse durations less than 20 ns. 6. Full Device AC operation requires linear VCC ramp from 0 to VCC(min) > 500 s.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Capacitance[7, 8]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ) Max. 12 12 Unit pF pF
Thermal Resistance[7]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
AC Test Loads and Waveforms
R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT RTH OUTPUT V 2.5V (2.2V to 2.7V) 16667 15385 8000 1.20 3.0V (2.7V to 3.6V) 1103 1554 645 1.75 Unit V
Parameters R1 R2 RTH VTH
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC= 1.5V CE1 > VCC-0.2V, CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V L LL 0 tRC Conditions Min. 1.5 30 25 ns ns Typ.[3] Max. Unit V A
tCDR[7] tR[9]
Chip Deselect to Data Retention Time Operation Recovery Time
Notes: 7. Tested initially and after any design or process changes that may affect these parameters. 8. This applies for all packages. 9. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Data Retention Waveform[10, 11]
DATA RETENTION MODE VDR > 1.5V
VCC
CE or BHE.BLE
VCC, min. tCDR
VCC, min. tR
Switching Characteristics Over the Operating Range[11, 12]
55 ns Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD tDBE tLZBE tHZBE WRITE tWC tSCE tAW tHA tSA tPWE tBW tSD tHD tHZWE tLZWE CYCLE[15] Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE/BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[13, 14] WE HIGH to Low-Z[13] 10 55 40 40 0 0 40 40 25 0 20 10 70 60 60 0 0 45 60 30 0 25 ns ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to LOW OE HIGH to High CE LOW to Low Z[13] Z[13, 14] 10 20 0 55 55 10 20 5 25 0 70 70 5 20 10 25 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 ns Max. Unit
Z[13]
CE HIGH to High Z[13, 14] CE LOW HIGH to Power-Up CE HIGH to Power-Down BLE/BHE LOW to Data Valid BLE/BHE LOW to Low Z[13] BLE/BHE HIGH to HIGH Z[13, 14]
Notes: 10. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. 11. CE is the logical combination of CE1 and CE2. When CE1 is LOW and CE2 is HIGH, CE is LOW; when CE1 is HIGH or CE2 is LOW, CE is HIGH. 12. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 ns/V, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH as shown in the "AC Test Loads and Waveforms" section. 13. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 14. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 15. The internal Write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)[16, 17] tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle 2 (OE Controlled)[11, 17, 18]
ADDRESS tRC
CE
tPD tHZCE tACE
BHE/BLE
tLZBE
OE
tDBE
tHZBE
DATA OUT VCC SUPPLY CURRENT
tLZOE HIGH IMPEDANCE tLZCE tPU
tDOE DATA VALID
tHZOE HIGH IMPEDANCE ICC ISB
50%
50%
Notes: 16. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 17. WE is HIGH for read cycle. 18. Address valid prior to or coincident with CE, BHE, BLE transition LOW.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle 1 (WE Controlled)[11, 15, 19, 20, 21] tWC ADDRESS tSCE
CE
tAW tSA
WE
tHA tPWE
BHE/BLE
tBW
OE
tSD DATA I/O
See Note 21
tHD
VALID DATA tHZOE
Write Cycle 2 (CE Controlled)[11, 15, 19, 20, 21] tWC ADDRESS tSCE CE
tSA
tAW tPWE
tHA
WE tBW
BHE/BLE
OE tSD DATA I/O
See Note 21
tHD
VALID DATA t
HZOE Notes: 19. Data I/O is high impedance if OE = VIH. 20. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high-impedance state. 21. During this period, the I/Os are in output state and input signals should not be applied.
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Switching Waveforms (continued)
Write Cycle 3 (WE Controlled, OE LOW)[11, 20, 21] tWC ADDRESS tSCE
CE
BHE/BLE
tBW tAW tSA tPWE tHA
WE
tSD DATA I/O
See Note 21
tHD
VALID DATA tHZWE tLZWE
Write Cycle 4 (BHE/BLE Controlled, OE LOW)[11, 20, 21] tWC ADDRESS CE tSCE tAW BHE/BLE tSA WE tPWE tSD DATA I/O
See Note 21
tHA tBW
tHD
VALID DATA
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Truth Table
CE1 H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0-I/O15) Data Out (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data Out (I/O8-I/O15) High Z High Z High Z Data In (I/O0-I/O15) Data In (I/O0-I/O7); High Z (I/O8-I/O15) High Z (I/O0-I/O7); Data In (I/O8-I/O15) Mode Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Power Standby (ISB) Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC)
Ordering Information
Speed (ns) 55 Ordering Code CY62177DV30L-55BAI CY62177DV30LL-55BAI CY62177DV30LL-55BAXI 70 CY62177DV30L-70BAI 51-85191 48-ball FBGA (8 mm x 9.5mm x 1.2 mm) (Pb-free) 48-ball FBGA (8 mm x 9.5mm x 1.2 mm) Industrial Package Diagram 51-85191 Package Type 48-ball FBGA (8 mm x 9.5mm x 1.2 mm) Operating Range Industrial
Document #: 38-05633 Rev. *C
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CY62177DV30 MoBL(R)
Package Diagram
48 FBGA (8 x 9.5 x 1.2 MM) (51-85191)
BOTTOM VIEW TOP VIEW O0.05 M C O0.25 M C A B A1 CORNER O0.300.05(48X) 1 2 3 4 5 6 6 5 4 3 2 1 A1 CORNER
A B 9.500.10 0.75 C 9.500.10 5.25 D E F G H
A B C D E 2.625 F G H
A B 8.000.10
A
1.875 0.75 3.75 B 8.000.10
0.65 MAX.
0.25 C
0.210.05
0.15 C
0.15(4X)
51-85191-**
SEATING PLANE 0.26 MAX. C 1.20 MAX
UNLESS OTHERWISE SPECIFIED
ALL DIMENSIONS ARE IN MILLIMETERS STANDARD TOLERANCES ON: DECIMALS + .XX .XXX .XXXX + + -
DESIGNED BY
DATE
DRAWN ANGLES + -
DATE
HTN
CHK BY
06/25/03
DATE
CYPRESS Company Confidential
TITLE
APPROVED BY
DATE
48 FBGA (8x9.5x1.2MM) PACKAGE OUTLINE
PART NO. DWG NO
MATERIAL
APPROVED BY DATE
SIZE
FINISH
AINS INFORMATION WHICH IS THE PROPRIETARY PROPERTY OF CYPRESS COMPANY. THIS DRAWING IS ENCE AND ITS CONTENTS MAY NOT BE DISCLOSED WITHOUT WRITTEN CONSENT OF CYPRESS COMPANY.
A
SCALE
BA48J
1: 1
51-85191
SHEET
MoBL is a registered trademark and More Battery Life is a trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders
Document #: 38-05633 Rev. *C
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62177DV30 MoBL(R)
Document History Page
Document Title:CY62177DV30 MoBL(R) 32-Mbit (2M x 16) Static RAM Document #: 38-05633 REV. ** *A ECN NO. Issue Date 251075 330363 See ECN See ECN Orig. of Change AJU AJU Description of Change New Data Sheet Changed title of data sheet from CYM62177DV30 to CY62177DV30 Added second chip enable (CE2) Added footnote #12 on page 5 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Changed ISB1 from 60 and 40 A to 100 A for the L and LL versions for both the 55 and the 70 ns speed bins respectively. Converted from Preliminary to Final Changed the ISB2(Max) from 40 A to 50 A for LL version of both 45 ns and 55 ns speed bins Changed the ICCDR(Max) from 20 A to 25 A for LL version Updated the Ordeing Information table
*B
400960
See ECN
NXR
*C
469187
See ECN
NXR
Document #: 38-05633 Rev. *C
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